 |
Northern California |
|
|
|
Transistors and Isolation for Advanced Semiconductor Products Dr. Michael C. Smayling Applied Materials, Inc. Introduction The electronics industry has been able to deliver remarkable product improvements primarily due to the feature size scaling of semiconductor devices. In particular, MOS transistors have been the device-of-choice for VLSI and ULSI integrated circuits. Transistor gate lengths have shrunk from ~3mm used in the early 1980‰s to ~0.2mm in production today. This scaling trend, forecast by Gordon Moore in 1965, has driven memory bit-density from 64K to 64M per chip over the past 20 years with a continually decreasing bit cost. IC Basics The building blocks for logic chips are the CMOS inverter and NAND/NOR gates. The performance of full chips depends on the capability of gates and inverters, determined by FEOL (Front End of Line) processing, and how the gates are interconnected, determined by BEOL (Back End of Line) processing. For a CMOS inverter, different "views" are important to different members of a chip development team. The logic designers consider a Boolean-element view, represented by a logic symbol and a truth table. Circuit designers use a schematic view and layout view. Process designers use the layout view and a cross-section view. Transistor Structure Trends MOS transistor structures have become more complex with the scaling of gate length. Simple single implant source/drains have evolved through double-diffused and lightly-doped drains to multiple implant, multiple pattern, multiple species structures. Silicides were introduced to reduce series resistance and contact resistance in the source/drain regions. The channel region has undergone a similar trend toward more complexity, from single implant VT adjusts to multiple implants for VT, punchthrough, and short-channel-effect control. The gate structure has evolved from metal gates to polysilicon gates to polysilicon plus silicide gates and perhaps eventually back to metal gates. Each of these material changes has required development of new material deposition and etch equipment and processes. The gate dielectric has also changed, from furnace-grown silicon dioxide to rapid-thermally processed oxide to nitrided oxide and in the near future higher-k materials like silicates. Linking Customer Specs to Transistor Structures Chip customers typically have many specs, but for logic chips the key parameters are frequency, power (active and/or standby), reliability, and cost. It is the challenge of the chip development team to meet the customer requirements within constraints imposed by materials and "laws of nature." The evolution in transistor structure has been driven by changes in all four of the key parameters. |
|
[HOME][National
AIChE] [Contact Us] [Notify
You if this Page Changes] |