Sameer Parab
Elantec Semiconductor,
Milpitas, CA

Introduction and Issues: In this paper, we discuss the recent advances in bipolar transistor technology development. Bipolar transistor technology faces a growing market in high-speed amplifiers, telecommunications, video amplifiers and optical storage drivers. Complementary bipolar transistors [NPN and PNP] allow for design of optimized products for mixed signal, AC and high-speed applications. The classical process technologies for complementary bipolar transistors were based on Junction Isolation and Di-electric Isolation to isolate the various devices. These technologies will struggle to meet the high demands on speed required in future applications due to high capacitances inherent in the transistor structures. We aim to present advanced analog bipolar transistor structure processing and compare improvements in speed and performance characteristics with those offered by older technologies.

Technology Outlook: The bipolar transistor performance enhancements can be studied by segmenting two main categories of the transistor structure – active components and parasitic effects. The active components consist of the three terminals called the Emitter, Base and Collector. We present the classical optimization techniques to achieve maximum performance from a given active configuration of emitter, base and collector. We illustrate how transistor parameters such as Emitter Resistance, Intrinsic and Extrinsic Base Resistance, Collector resistance and Base width contribute to achieving higher speeds for a given voltage of the process. We further discuss in detail the advances in active components with processing innovations such as Poly-silicon emitters[1] and Silicon-Germanium bases.[2] We explain the principles underlying the processing modifications that allows to achieve higher speeds and better performance than those offered by classical processes.

The advances in reducing parasitic effects are illustrated by comparing classical device structures such as junction-isolated transistors to novel Silicon-On-Insulator [SOI] technologies[3]. The older junction isolation [JI] processes use heavily doped junctions to isolate various devices. These junctions have their own capacitances and these capacitances vary with voltage. Circuits have to be carefully designed to avoid latch-up problems where the depletion regions in the junctions can start interacting with each other. The transistor speeds are also lower since the parasitic capacitances due to these junctions are higher. The di-electric isolation process overcomes this problem by having an insulator such as silicon dioxide to completely isolate the device. The thickness of the oxide can be chosen to minimize the capacitance. We show that for a given transistor design with identical active components, the advanced ‘SOI’ processes offer higher speeds due to reduced parasitic effects.

Conclusions: We summarize the performance enhancements in transistors offered by advanced analog processes. We show strategies to integrate active components and parasitic effects using advanced process technologies to process bipolar transistor structures that can meet the performance demands in the 21^st century.

3. Auberton-Herve, J., Nishimura, T., "SOI-based Devices", Solid State Technology, July 1994.